The invention relates generally to electronic memory. More particularly, the invention relates to a method and apparatus for sensing a state of memory cells.
Computing devices require memory. The memory can include read only memory (ROM) or random access memory (RAM). Generally, memory includes memory cells that are arranged in rows and columns. The individual memory cells are accessed through the use of row select lines and column select lines, typically referred to as word lines and bit lines.
FIG. 1 shows an array of random access memory (RAM) cells 110, a row decoder 120, a column decoder 130 and associated sense amplifiers 140. The row decoder 120 selects a row of the array of RAM cells 110 through a word line (WL). The column decoder 130 selects a column of the array of the RAM cell 110 through a bit line (BL). Generally, the sense amplifiers 140 are connectable to the bit lines. The sense amplifiers 140 provide sensing of states of the memory cells.
In a resistive RAM array, the resistance of each memory cell has more than one state. The data in a memory cell can be determined by measuring a resistive state of the cell. The resistive memory cells may include magnetic layers, a fuse or anti-fuse, or any element that stores information affecting a magnitude of a nominal resistance of the memory cell.
Magnetic random access memory (MRAM) is a type of resistive memory. MRAM can include a resistive cross point array of spin dependent tunneling (SDT) junctions. Each SDT junction memory element is located at a cross point of a word line and a bit line. The magnetization of each SDT junction assumes one of two stable orientations at any given time. These two stable orientation, parallel and anti-parallel, represent logic values of xe2x80x9c0xe2x80x9d and xe2x80x9c1.xe2x80x9d The magnetization orientation affects the resistance of the SDT junction. The resistance of the SDT junction is a first value if the magnetization orientation is parallel and a second value if the magnetization orientation is anti-parallel. The magnetization orientation of the SDT junction, and therefore, its logic value may be determined by sensing the resistance of the SDT junction.
Generally, sensing the resistance of an SDT junction requires sensing relatively small signals. The resistance, and therefore, the logical state of an SDT junction can be determined by applying a voltage across the SDT junction and sensing the resultant current, or by applying a current through the SDT junction and sensing the resulting voltage across the SDT junction. SDT junctions include physical characteristics that require sensing either a small amplitude sense current, or a small amplitude sense voltage.
Due to the small signal levels, MRAM sense amplifiers provide output signals that are much smaller in amplitude that most memory sense amplifiers. Therefore, signal noise and interference must be minimized. MRAM circuitry selects and isolates individual MRAM memory cells within large two-dimensional arrays of MRAM cells. MRAM sense amplifiers rely on minimal signal noise and interference. Minimizing the MRAM sense amplifier noise and interference improves the reliability and performance of the MRAM sense circuits.
MRAM memory can include digital support circuitry. Digital circuitry can generate transient signals that can cause noise and distortion to couple to the MRAM memory cells, which can introduce noise and distortion to sensed MRAM signals.
It should be noted that other types of RAM (for example, SRAM and DRAM) do not require the signal noise and interference minimization required by MRAM, because other types of memory generally operate with much larger sense signals.
It is desirable to have a method and apparatus for sensing memory that provides for minimal sensing signal noise and interference.
The invention includes an apparatus and method for minimizing noise and interference of RAM sensed signals. The method and apparatus are adaptable for use with MRAM.
An embodiment of the invention includes a memory cell sensing system. The memory cell sensing system includes a plurality of memory cells located on a first plane of an integrated circuit. The system further includes a plurality of sense amplifiers located on a sense plane that is adjacent to the first plane. Each sense amplifier is connectable to at least one memory cell based upon a relative location of each sense amplifier with respect to locations of the at least one memory cell.
Another embodiment of the invention includes a method of sensing a state of a selected memory cell within a plurality of memory cells. A plurality of the memory cells are located on a first plane of an integrated circuit. A plurality of sense amplifiers are located on a sense plane that is adjacent to the first plane. The method includes connecting a sense amplifier to at least one memory cell based upon a relative location of each sense amplifier with respect to locations of the at least one memory cell.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.